RISKS ARE NOTABLY increasing in the design of complex SoCs at the 65-nm technology node and beyond. Escalating design costs, increasing profitability and time-to-market pressures, and skyrocketing power consumption in conjunction with a lower first-silicon success rate, and lower chip manufacturability and reliability are among the key challenges that chip makers are confronting. To minimize th...

We propose a novel Design for Testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as s...

Nurses need to think critically and respond to a wide variety of clinical situations. Simulations can provide realistic examples of typical clinical situations to undertake learning of complex skills in a less threatening environment. The teacher is thus provided with more control over the learning environment, resulting in a situation which is beneficial in knowledge and skill acquisition. In ...