We consider binary search trees, where rebalancing transformations need not be connected with updates but may be delayed. For standard AVL tree rebalancing, we prove that even though the rebalancing operations are un-coupled from updates, their total number is bounded by O(M log(M +N)), where M is the number of updates to an AVL tree of initial size N. Hence, relaxed balancing of AVL trees come...

Electronic Stacked integrated circuits presents many advantages like short latency, low power consumption, and immense amount of bandwidth delivered by Through Silicon Vias (TSV). However, these circuits present many test issues, designer must ensure that each of individual die layer is designed to be testable before bonding take places. In this paper we propose a novel technique of Design for ...

This paper describes the CMOS standard cells characterization methodology for IDDQ testing. Defect statistics was taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimenta...

The paper presents why AUTOSAR conformance tests are required, what has been achieved, and how 3 car manufacturers will use conformance tests as part of their vehicle E/E engineering process. Important topics covered are the need for conformance testing when developing a standard, the relationship between conformance and interoperability, the need for interoperability of ECUs in a vehicle, and ...

Kernel Methods are a class of algorithms for pattern analysis with a number of convenient features. They can deal in a uniform way with a multitude of data types and can be used to detect many types of relations in data. Importantly for applications, they have a modular structure, in that any kernel function can be used with any kernel-based algorithm. This means that customized solutions can b...

This work presents the design methodology and the architecture of simple, efficient and easy-to-use test circuits for evaluating and validating any set of library cells (combinational and sequential logic gates), both in the design environment and for on silicon prototyping. Evaluation and validation are accomplished considering functionality, performance, power consumption and impact in operat...

This document specifies tests to determine if multiple independent instantiations of a performance-metric RFC have implemented the specifications in the same way. This is the performance-metric equivalent of interoperability, required to advance RFCs along the Standards Track. Results from different implementations of metric RFCs will be collected under the same underlying network conditions an...