Power consumption and delay are two important considerations for VLSI systems. prime motive of this project is to reduce the power and to get less delay that is nothing but the high speed for any design. So Adder is one of the fundamental blocks present in arithmetic logic unit (ALU), floating point unit. Adders are very important components in some other applications such as microprocessor and...

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips very high density, has recently led rapid and inventive progresses low-power design. most effective technique is adiabatic logic circuit design energy-efficient hardware. This paper presents two approaches for the low circuits, modified positive feedback (modified PFAL) other direct cu...

In this paper propose a new high performance 1 bit full adder cell using XOR/XNOR gate design style as well as lower power consumption. Simulation results illustrate the superiority of the resulting proposed adder against conventional 1-bit full-adder in terms of power consumption improvement performance (98% of 10T, 47% of 14T & 16T), propagation delay and PDP. We have performed simulations us...

We use surface tension-based passive pumping and fluidic resistance to create a number of microfluidic analogs to electronic circuit components. Three classes of components are demonstrated: (1) OR/AND, NOR/NAND, and XNOR digital microfluidic logic gates; (2) programmable, autonomous timers; and (3) slow, perfusive flow rheostats. The components can be implemented with standard pipettes and pro...

In this paper we propose new three-input XOR and three-input XNOR gate based on generalized threshold gate (GTG) topology. The GTG topology is main part is monostable-bistable logic element (MOBILE). The proposed gates use fewer elements count in comparison with other implementations which utilize MOBILE as a main structure. By exploiting the new three-input XOR gate and a carry generator, we p...

A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power dissipation has been cut down to a minimum while providing the full output voltage swing at all nodes in the circuit. Furthermore, the complete circuit is implemented with a bare minimum of 28 transistors.

The main goal of this paper is to analyze the general problem of using Convolutional Neural Networks (CNNs) in robots with limited computational capabilities, and to propose general design guidelines for their use. In addition, two different CNN based NAO robot detectors that are able to run in real-time while playing soccer are proposed. One of the detectors is based on the XNOR-Net and the ot...

Experimental Realization of Topologically-Protected All-Optical Logic Gates Based on Silicon Photonic Crystal Slabs In article number 2200329, Furong Zhang, Lu He, Huizhen Xiangdong and colleagues present the experimental realization topologically-protected all-optical logic gates Chips. All major functions (OR, XOR, NOT, XNOR, NAND, NOR, AND) can be realized even if some disorders exist. These...