The CryptoBooster is a modular and reconfigurable cryptographic coprocessor that takes full advantage of current high-performance reconfigurable circuits (FPGAs) and their partial reconfigurability. The CryptoBooster works as a coprocessor with a host system in order to accelerate cryptographic operations. A series of cryptographic modules for different encryption algorithms are planned. The fi...

Intel R © Xeon Phi TM coprocessors are capable of delivering more performance and better energy efficiency than Intel R © Xeon R © processors for certain parallel applications. In this paper, we investigate the porting and optimization of a test problem for the Intel Xeon Phi coprocessor. The test problem is a basic N-body simulation, which is the foundation of a number of applications in compu...

This paper presents preliminary results on the design of an Object Coprocessor (OCP) cooperating with a RISC– architecture processor (ARM7, by Advanced RISC Machines Ltd.). This coprocessor implements in hardware some low–level processing and control steps required by the object–oriented model. The processor and the OCP constitute a processing architecture whose extended instruction set feature...

Cryptography plays an important role for data security and integrity and is widely adopted, especially in embedded systems. On one hand, we want to reduce the computation overhead of cryptography algorithms; on the other hand, we also want to reduce the energy consumption associated with this computation overhead. In this paper, we explore techniques to improve the overall throughput and energy...

New analytical and the speedup models for evaluating the performance of a generic reconfigurable coprocessor (RC) system are presented. We present a generic performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a sys...

The Garp project [3] quantitatively investigates the benefits of adding an on-chip dynamically reconfigurable coprocessor to a standard instruction processor. Intended for acceleration of loops, Garp’s coprocessor performs iteration control and both streaming and random memory accesses without assistance from the instruction processor. The companion project Garpcc [2] investigates whether new c...

Hardware/software co-design of computationally intensive cryptosystems is the preferred solution to achieve the required speed for resource-limited embedded applications. This paper presents a microcode instruction set coprocessor which is designed to work with 8bit microcontrollers to implement a hyperelliptic curve cryptosystem. The microcode coprocessor is capable of performing a range of Ga...

In Private Information Retrieval (PIR), a user obtains one of N records from a server, without the server learning what record was requested. Recent research in “practical PIR” has limited the players to the user and server and limited the user’s work to negotiating a session key (eg. as in SSL)— but then added a secure coprocessor to the server and required the secure coprocessor to encrypt/pe...

Monitoring power quality (PQ) indicators is an important part of modern grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures voltage fluctuations. In state-of-the-art measuring devices, the measurement channel usually implemented as a dedicated processor subsystem. Implementation IEC 61000-4-15 compliant algorithm requires significant amount ...