OF THE THESIS Novel Flip-Flop Designs Tolerant to Soft-Errors and Crosstalk Effects by Aditya Jagirdar Thesis Director: Prof. Michael L. Bushnell The desire to make technology faster, smaller and more affordable compels us to shrink transistors further. As we realize designs with millions of transistors, most of the existing problems increase in severity and newer problems crop up. One major ne...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we present the concept of flip-flop featuring embedded Threshold Logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such Threshold Logic flip-flops, obtained in 0.25pm CMOS technology. It is shown in thi...

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed h...

Clustered voltage scaling scheme is an effective method of power consumption reduction without performance degradation. One of the main issues in this scheme is performance and power penalties due to insertion of level converting flip-flops at the interface from low-supply to high supply clusters to simultaneously perform latching and level converting functions. A new level converting flip-flop...

Quantum dot cellular automata (QCA) introduces a pioneer technology in nano scale computer architectures. Employing this technology is one of the solutions to decrease the size of circuits and reducing power dissipation. In this paper, two new optimized FlipFlops with reset input are proposed in quantum dot cellular automata technology. In addition, comparison with related works is performed.Th...

In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switc...

As the CMOS device becomes smaller, the process and aging variations become one of the major issues for circuit reliability and yield. Thus, a number of studies on the aging effects are currently underway. In this paper, we measure the setup/hold time and the variations considering aging effects such as a hot carrier injection (HCI) and negative bias temperature instability (NBTI) on flip-flop....

The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. T...