The RICH detector in CBM shall provide electron identification together with the TRD detectors for the measurement of low-mass vector mesons and charmonium in the di-electron decay channel. Both observables are considered key probes for the study of compressed baryonic matter in heavy ion collisions. A RICH design based on first general considerations has been developed and studied in detector ...

This article presents an optimization model of the quantifiable aspects of architectural floorplan layout design, and a companion article presents a method for integrating mathematical optimization and subjective decision making during conceptual design. The model presented here offers a new approach to floorplan layout optimization that takes advantage of the efficiency of gradient-based algor...

geographic information systems (gis) are one of the fastest growing computer-based technologies of past two decades, yet, full potential of this technology in construction has not been realized. based upon gis capabilities, construction site layout is one of the areas that gis could be applied. the layout of temporary facilities (tfs) such as warehouses, fabrication shops, maintenance shops, co...

GONG, ZHENHUAN. Multi-level Data Layout Optimization for Heterogeneous Access Patterns. (Under the direction of Dr. Nagiza F. Samatova.) Recent years have seen an enormous increase in computation power of leadership computing facilities. As a result, huge amounts of data, from terascale to petascale, are being produced by scientific applications running on supercomputers. However, the I/O subsy...

We describe the music renotation problem, in which one transforms a collection of recognized music notation primitives (e.g. note heads, stems, beams, flags, clefs, accidentals, etc.) into a different notation format, such as transposing the notation or displaying it in a rectangle or arbitrary size. We represent a limited degree of image understanding through a graph that connects pairs of sym...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...