| The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can nd practical applications in ne-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A new factorization algorithm for AND/OR/EXOR logic with multi-valued literals is introduced, that has application to minimization of Logic Cell Array...

CMOS chips having high leakage are observed to have high burn-in fallout rate. IDDQ testing has been considered as an alternative to burn-in. However, increased subthreshold leakage current in deep sub-micron technologies limits the use of IDDQ testing in its present form. In this work, a statistical outlier rejection technique known as the median of absolute deviations (MAD) is evaluated as a ...

{ As IC fabrication capabilities extend down to sub-half-micron, the signiicance of interconnect delay and power dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools have not been able to solve the problem. The only remaining alternative is that tradeoos in logical and physical domains must be addressed in an integrated manner. Vast business opportu...

The cross-integration of spin-wave and superconducting technologies is a promising method for creating novel hybrid devices future information processing to store, manipulate, or convert data in both classical quantum regimes. Hybrid magnon-polariton systems have been widely studied using bulk Yttrium Iron Garnet (Y$_{3}$Fe$_{5}$O$_{12}$, YIG) three-dimensional microwave photon cavities. Howeve...

The size and shape of the lens fibres were estimated by specular reflex photography. The fibres were measured in three separate regions. Peripheral fibres have a mean width of 10.2 micron, the central fibres 11.9 micron, and the central fibres with suture 15.8 micron. Measurements were made of the taper (becoming narrower towards the suture) and flare (becoming wider towards the suture). The pe...

Many physical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. Such approaches are extremely e ective at reducing cross-talk at circuit speeds where inductive e ects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive cross-talk e ects are substantial in long bu...

| The proposed factorization methods for regular arrays of two-input cells have several important advantages over the existing logic representations and methodologies: (1) The logic representation and design implementation are consistent. (2) The stages of logic synthesis and physical design are eeectively merged into a single stage. (3) The structure of the mapping solution is a regular rectan...

As IC fabrication capabilities ex tend down to sub half micron the signi cance of interconnect delay and power dissipation can no longer be ignored Existing enhancements to synthesis and physical design tools have not been able to solve the problem The only re maining alternative is that tradeo s in logical and physical domains must be addressed in an integrated manner Vast business opportuniti...

Before the CMOS process is scaled into deep sub-micron process, dynamic energy loss has always dominated power dissipation, while leakage power is little. The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, thus the MOS devices will no longer be totally turned-off anymore. The power dissipation caused by leakage current ca...

With resent advances of Deep Sub Micron technologies, the floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. In this paper, we propose a novel constraint driven floorplanning technique based on Genetic Algorithm (GA). Many works have done for the floorplanning problem using GA. However, no studies have ever ...