Semiconductor supply chain is increasingly getting exposed to variety of security attacks such as Trojan insertion, cloning, counterfeiting, reverse engineering (RE), piracy of Intellectual Property (IP) or Integrated Circuit (IC) and side-channel analysis due to involvement of untrusted parties. In this paper, we propose transistor threshold voltage-defined switches to camouflage the logic gat...

Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as 10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder implementation and, as a result, the delay time and power dissipation are sign...

Abstract Recent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density energy consumption. Individual design, optimized interconnects, careful material selection are key factors determining the o...

The Content addressable Memory (CAM) is high speed memories that are used in high speed networks, lookup tables and so on. The data to be searched will be compared with the data stored in the CAM cell and the address of the cell will be returned for the matched data. The parallel search operation in the memory is the important feature which improves the speed of search operation in CAM cells. H...

In this study, a minimum set of low-power digital standard cells for low-leakage applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and flip-flop. The inverter, NAND, NOR and flip-flop standard cells based on the gate-length biasing technique are...

Received Apr 24, 2016 Revised Aug 3, 2016 Accepted Aug 18, 2016 In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR an...

Dual Forms of Reed–Muller (DFRM) are implemented in OR/XNOR forms, which are based on the features of coincidence operation. Map folding and transformation techniques are proposed for the conversion between Boolean and DFRM expansions. However, map techniques can only be used for up to 6 variables. To overcome the limitation, serial tabular technique (STT) and parallel tabular technique (PTT) a...

In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...