We present an optical shift register that consist out of two serially connected optical flip-flop memories driven by common clock pulses. Each optical flip-flop consists out of two ring lasers sharing a single active element, which makes the optical flip-flops easily cascade with each other. The two cascaded optical flip-flops are controlled by the clock pulses in such a way that the input data...

In this paper, based on the coupled-mode and carrier rate equations, derivation of a dynamic model and numerically analysis of a MQW chirped DFB-SOA all-optical flip-flop is done precisely. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the DFB-SOA all optical flip flop. We have shown that strained MQW a...

Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get “optimized” to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circui...

Fatty acid (FA) uniport via mitochondrial uncoupling protein (UcP) was detected fluorometrically with PBFI, potassium-binding benzofuran phthalate and SPQ, 6-methoxy-N-(3-sulfopropyl)-quinolinium, indicating K+ and H+, respectively. The FA structural patterns required for FA flip-flop, UcP-mediated FA uniport, activation of UcP-mediated H+ transport in proteoliposomes, and inhibition of UcP-med...

Flip-Flop_1: Firstly, the old flip-flop construction that we choose to implement is the classic single edge triggered flip-flop (SETFF) which is shown in FIGURE 10.24 in the book " CMOS VLSI Design A Circuits and Systems Perspective " 4th Edition. The figure is shown below. Fig A-1 Resettable Flip-Flop The schematic that we construct is shown as follows: Fig A-2 Resettable Flip-Flop Schematic T...

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...

Cholesterol (CHOL) molecules play a key role in modulating the rigidity of cell membranes and controlling intracellular transport and signal transduction. Using an all-atom molecular dynamics approach, we study the process of CHOL interleaflet transport (flip-flop) in a dipalmitoylphosphatidycholine (DPPC)-CHOL bilayer over a time period of 15 μs. We investigate the effect of the flip-flop proc...

In this paper a novel low power double edge pulse triggered flip flop (FF) design is present. First, the pulse generation control logic by using the NAND function and is removed from the critical path to facilitate a faster discharge operation. A simple two transistor NAND gate design is used to reduce the circuit complexity. Second, a double edge conditional discharging flip flop is used to re...

In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes mu...

This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...