MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si0 4Ge0 6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily usi...

In the present paper we have done a comparative analysis of Dual Gate MOSFET having split gate architecture and conventional Dual Gate MOSFET architecture. Simulations have been performed using SILVACO-ATLAS tool, which shows significant improvement in characteristic of split gate architecture in comparison to the conventional structure. The split gate architecture consist two different materia...

The physical dimensions of bulk MOSFETs have been aggressively scaled down and these conventional devices will soon be experiencing limited improvements due to the scaling down. In order to continue performance improvements, new device architectures are needed. As the scaling of MOSFET into sub-100nm regime, SOI and DG-MOSFET are expect to replace traditional bulk MOSFET. These novel MOSFET dev...

The decision to use a commercial power MOSFET in a harsh radioactive environment[1], such as outer space, is subordinated to the capacity of the device to tolerate single event effects (SEE)[2] caused by single ionising particles. An incident ion may trigger charge generating mechanisms in the active volumes of the device that may give rise to a simple momentary malfunction or to a destructive ...

Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...

With CMOS scaling into the Sub-100nm regime, the supply and the threshold voltages need to be scaled proportionately. This necessitates addressing of low power CMOS device design issues. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to addressing the problems associated with device scaling for low power CMOS. This work focuses on the ...

A reconfigurable transistor that can act both as a ntype and as a p-type MOSFET presents a flexibility of operation that may enable better circuit design [1]. Many options use sophisticated fabrication processes and architectures such as nanowires [2,3,4] to obtain a reconfigurable transistor. There are papers that report simulation results [5,6] for this kind of device. In this work we introdu...

In this article, a novel concept is introduced to improve the radio frequency (RF) linearity of partially-depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free c...

The key to successfully applying the SiC MOSFET requires an understanding of the device’s unique operating characteristics. In this section, the characteristics of Cree’s 1200V 80mΩ SiC MOSFET (CMF20120D) will be discussed. Comparisons will be made with other similar silicon devices along with application implications. The intention of this comparison is to illustrate the differences in operati...

Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by u...