Verifying a 64-bit multiplier has a computational complexity that puts it beyond the grasp of current nite-state algorithms, including those based upon homomorphic reduction, the induction principle, and bdd xed-point algorithms. Theorem proving, while not bound by the same computational constraints, may not be feasible for routinely coping with the complex, low-level details of a real multipli...

In this paper a 64-bit double precision floating point multiplier is implemented. A BIST test pattern generator for double precision multiplier is proposed. Linear feedback shift registers are used to generate the test pattern. A comparator is used to compare the output response and the expected response. For the circuit to work correctly the output response must be the same as the expected res...

Verifying a 64-bit multiplier has a computational complexity that puts it beyond the grasp of current finite-state algorithms, including those based upon homomorphic reduction, the induction principle, and bdd fixed-point algorithms. Theorem proving, while not bound by the same computational constraints, may not be feasible for routinely coping with the complex, low-level details of a real mult...

Elliptic Curve Cryptography is one of the most preferred public key Cryptography algorithms known for its security strength and reduced key size. This makes ECC most suitable for implementing the hardware security chip for providing security services in portable embedded devices. This paper presents an area efficient Security Chip housing ECC algorithm for data encryption over binary field and ...

As FPGA densities have increased, the feasibility of using floatingpoint computations on FPGAs has improved. Moreover, recent innovations in FPGA architecture have changed the design tradeoff space by providing new fixed circuit functions which may be employed in floating-point computations. These include high density multiplier blocks and shift registers. This paper evaluates the use of such b...

Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture beco...

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental ...