Abstract: This study is carried out to describe the behaviour of vehicles flow on the road, in the presence of blocking effects. A non-linear three dimensional system of ordinary differential equations is used to describe vehicles flow on the road. The study classify total vehicles population on the road into three compartments as Free – Slow – Released vehicles. The formulated model is well-po...

We investigate the communication capacity and optimal data transmission schedules for processor networks connected by communication links, for example Transputer clusters. Each link allows the two processors at its endpoints to exchange data with a given xed transmission rate d. The communication itself is done in a blocking mode, that means the two processors have to synchronize before startin...

The performance of statically scheduled VLIW processors is highly sensitive to the instruction scheduling performed by the compiler. In this work we identify a major deficiency in existing instruction scheduling for VLIW processors. Unlike most dynamically scheduled processors, a VLIW processor with no load-use hardware interlocks will completely stall upon a cache-miss of any of the operations...

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...

We introduce a method for improving the cache performance of irregular computations in which data are referenced through run-time defined indirection arrays. Such computations often arise in scientific problems. The presented method, called Run-Time Reference Clustering (RTRC), is a run-time analog of a compile-time blocking used for dense matrix problems. RTRC uses the data partitioning and re...

Multithreading can be used to hide latency in a non-blocking cache architecture. By switching execution form one thread to another, the CPU can perform useful work, while waiting for pending requests to be processed by the main memory. This frequent context switching however, produces a very irregular memory referencing pattern. In this paper we examine the effects of associativity and block si...

Buffered coscheduling is a new methodology that can substantially increase resource utilization, improve response time, and simplify the development of the run-time support in a parallel machine. In this paper, we provide an in-depth analysis of three important aspects of the proposed methodology: the impact of the communication pattern and type of synchronization, the impact of memory constrai...

Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority (HP) or at the lowest priority on the processor (LP), respectively. Based on this view, previously we have ...

Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of magnitude performance improvement over more traditional communication libraries. It is used by library and compiler writers to obtain the utmost performance and has been used to implement the novel parallel language Split-C. This paper discusses the experience we gai...