This paper presents an 3.5 GHz low noise amplifier that uses a two-stage configuration, using 0.35 m AlGaN/GaN HEMT on silicon substrate technology. The first stage has a cascode topology to achieve high gain, better stability and well reverse isolation. The second stage has a RC-feedback topology for wideband matching. The Tmatching network is used for broadband output matching. The results s...

A b s t r a c t Keywords: Cascode Topology Low Noise Amplifier Noise Figure Particle Swarm Optimization Design of a LNA is a complex process. Because it involves various parameters and needs complex trade-offs. This paper presents an optimized design of a low noise amplifier (LNA) using particle swarm optimization (PSO) technique. The proposed LNA has a cascode structure with inductive source d...

To proof low voltage techniques are valid in current conveyor design, Bulk driven and composite transistor (self cascode) techniques are used to get high performance results from CCII in low voltage supply. Conventional operational amplifier circuit from literature was our choice as core of the design. Our Focus with using low voltage techniques is study the frequency characteristics of a CCII ...

Abstract In this paper, a 12-bit 100MS/s digital-to-analog converter (DAC) is presented, where segmented current steering technique employed. A “4+8” architecture used compromising the advantages and disadvantages of binary-weighted thermometer-coded DACs. Cascode source cascode switch to achieve high input impedance minimize output glitches for good linearity dynamic performance. The simulatio...

Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This paper presents a new current mirror designed with FGMOS which exhibit high output imp...

A multiplexer is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. The low power circuits have become a top priority in modern VLSI design. This paper presents the power consumption comparisons and delay of various designs of 2:1 Multiplexer. The various logic styles such as Differential Cascode Voltage Switch Logic (DCVSL...

This paper presents the designing of a fully differential folded cascode operational transconductance amplifier (OTA) with common mode feedback circuit (CMFB). The designed OTA is operated in sub-threshold region to reduce the power consumption. The simulation is carried out in CADENCE environment using 150nm CMOS. The simulation result shows the DC gain of 82 dB with UGBW of 768 KHz, CMRR of 1...

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35μm standard CMOS technology. DC gain achieved is 56.7dB an...

The paper presents current adder and subtractor circuits based on cascode current mirror with improved linearity and wide linear range. The proposed circuits can be used for analog signal processing applications such as amplifiers, operational transconductance amplifiers (OTA), Gm-C filters, etc. In the proposed circuits, cascode current mirror topology is employed to improve current mirroring ...