In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder. Compared with previous work, this work reduces the hardware cost from two aspects. First, we reduce the logical costs of 1D IDCT by proposing a reordered parallel-in serial-out (RPISO) scheme. By using the RPISO scheme, we can reduce the required calculations for...

OpenMP is an implementation program interface that might be utilized to explicitly immediate multi-threaded and it shared memory parallelism. OpenMP platform for specifications multi-processing via concurrent work between interested parties of hardware and software industry, governments and academia. OpenMP is not needs implemented identically by all vendors and it is not proposed for distribut...

Reducing the decoding latency of turbo codes is important to real-time applications. Conventionally, (TC) runs in serial fashion, which means only one constituent soft decoders at a time. Parallel (PD) refers running parallel. Although it delivers output faster (compared (SD)), affects bit- and frame-error rates. This paper proposes procedure that combines both PD SD. It bridges two modes deter...

A parallel algorithm for the simulation of steady-state, two-dimensional flows of integral viscoelastic fluids on Multiple Instruction Multiple DATA (MIMD) computers with distributed memory is proposed. The algorithm has been implemented within the commercial finite element package POLYFMW developed at Louvain-la-Neuve and widely used in polymer processing applications. Parallel performance res...

In this paper, we consider the recovery of an airline schedule after an unforeseen event called disruption, making the planned schedule infeasible. We present a modeling framework that allows the consideration of operational constraints within a Column Generation (CG) scheme. We introduce the general concept of recovery network, generated for each individual unit of the problem, and show how un...

It is known that the strongly stable functions which arise in the semantics of PCF can be realized by sequential algorithms, which can be considered as deterministic strategies in games associated to PCF types. Studying the connection between strongly stable functions and sequential algorithms, two dual classes of hypercoherences naturally arise: the parallel and serial hypercoherences. The obj...

The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for Built-In Self Test, the extra area required for embedding testing structures can be cut down eflciently. Several schemes based on accumulators, subtracters, multipliers and shgt registers have been proposed and analyzed in the pa...

Serial decoding schedules for low-density parity-check (LDPC) codes are described and analyzed. Conventionally, in each iteration all the variable nodes and subsequently all the check nodes send messages to their neighbors (“flooding schedule”). In contrast, in the considered methods, the updating of the nodes is implemented according to a serial schedule. The evolution of the decoding algorith...