This paper gives an overview of the existing approaches to the hardware/software codesign of embedded systems. We discuss all the steps in the design trajectory. The common approach of adding dedicated hardware to accelerate the software (by way of a FPGA or ASIC coprocessor) is judged as not worth the effort. The multi-processor framework of ASIPs (application specific instruction set processo...

Application speedups can be achieved by speeding up the hardware, e.g. by utilising an Operating System co-processor. The paper present results from a comparison of executing benchmark programs on a system with and without a coprocessor, but which otherwise are identical. The observed speedup is mostly due to the fact that there is no need for clock tick administration, in the system with co-pr...

In this paper we will present a detailed study of implementing double-precision matrix-matrix multiplication (DGEMM) utilizing the Intel Xeon Phi Coprocessor. We discuss a DGEMM algorithm implementation running "natively" on the coprocessor, minimizing communication with the host CPU. We will run DGEMM across a range of matrix sizes natively as well using Intel Math Kernel Library. Our optimiza...

In this paper we present a system which enables easy and fast computation of Kohonen's selfor-ganizing map (SOM). It is a hardware supported system consisting of diierent parts. A neural coprocessor (COKOS) is connected to a personal computer (PC) by a special, asynchronous interface. The neural coprocessor works vector-component-parallel and processing-element-serial and speeds up the performa...

Heterogeneous computing systems involving the graphics processing unit (GPU) and other accelerators such as the coprocessor are playing an increasingly important role in scientific computing. However, none of the existing production Monte Carlo (MC) radiation transport codes were designed to take advantage of such heterogeneous computer architectures. In this paper, we describe the development ...

In this paper, we present a high-speed pairing coprocessor using Residue Number System (RNS) which is intrinsically suitable for parallel computation. This work improves the design of Cheung et al. [11] using a carefully selected RNS base and an optimized pipeline design of the modular multiplier. As a result, the cycle count for a modular reduction has been halved. When combining with the lazy...

A method was developed to increase the throughput of the Hewlett Packard, 98635A floating point processor equipped, model 236C computer. The increase was carried out in three phases each with a clock and or chip change during the modification. Two programs were written to test the results and evaluate the increases in performance made to the computer. The first one shows reduction in processing...

This paper describes an elementary protocol to prove possession of anonymous credentials together with its implementation on smart cards. The protocol uses self-blindable attribute certificates represented as points on an elliptic curve (which are stored on the card). These certificates are verified on the reader-side via a bilinear pairing. Java Card smart cards offer only very limited access ...

A field programmable gate array (FPGA) implementation of a coprocessor which uses the WSAT algorithm to solve Boolean satisfiability problems is presented. The input is a SAT problem description file from which a software program directly generates a problem-specific circuit design which can be downloaded to a Xilinx Virtex FPGA device and executed to find a solution. On an XCV300, problems of ...