In this paper, a double balanced radio frequency multiplier is presented which is customized for transmitted reference ultra wideband (UWB) receivers. The multiplier uses 90nm model parameters and exploits compensating transistors to provide controllable gain for a Gilbert core. After performing periodic and quasiperiodic non linear analyses the RF mixer (multiplier) achieves a voltage conversi...

applications such as digital spectrum analyzers, digital filtering, image processing, and video transmission need to compute the Discrete Fourier Transform (DFT). A Chip architecture to compute a 64point DFT using radix-4 algorithm every 18.87 μs at 100MHz clock rate is designed. This processor incorporates static memory, controller, and combinational operating unit (COU). Input data and output...

Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded Booth multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Non-uniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplicat...

This paper proves the Lp-boundedness of general bilinear operators associated to a symbol or multiplier which need not be smooth. The Main Theorem establishes a general result for multipliers that are allowed to have singularities along the edges of a cone as well as possibly at its vertex. It thus unifies ealier results of Coifman-Meyer for smooth multipliers and ones, such the Bilinear Hilber...

In this paper, transistor-level simulations of a detector called “cross-differentiate-multiplier demodulator (CDM)” are presented. This detector, which uses three blocks (a differentiator, a multiplier and a subtractor), is able to demodulate a received bit sequence, that was transmitted using a frequency-shift keying modulation scheme, with a bit rate equal to 20kbps. The application of this d...

We analytically investigated the feasibility of multiplier operation in the terahertz range for our original plasmon resonant photomixer. The photomixer features two unique structures (doubly interdigitated gate gratings and a vertical cavity) for higher radiation efficiencies. Its total field emission properties are the result of a combination of plasmon excitation dynamics and electromagnetic...

In this paper we present an FPGA implementation of a highspeed elliptic curve scalar multiplier for binary finite fields. High speeds are achieved by boosting the operating clock frequency while at the same time reducing the number of clock cycles required to do a scalar multiplication. To increase clock frequency, the design uses optimized implementations of the underlying field primitives and...

This paper presents a low-frequency amplitude modulator and demodulator based on Field Programmable Analogue Array (FPAA) devices. For creating the FPAA circuits, amplitude modulation and synchronous demodulation methods known from designing analogue RF transmission systems have been adapted. The proposed system allows redesigning the analogue conditioning stage thanks to the use of a FPAA devi...

This paper presents a rectifying antenna (rectenna) for the harvesting of the microwave energy associated to UHF (UltraHigh Frequency) Radio Frequency IDentification (RFID) systems. The proposed device uses a capacitively loaded T-shaped monopole with a coplanar waveguide feeding line as receiving antenna and a five-stage voltage multiplier as rectifier. Experimental results demonstrating an RF...

The Phase-Locked Loop (PLL) system is used extensively in modern electronic systems such as modems, mobile communications, satellite receivers and television systems. This work presents a method for modeling and simulation of second-order PLL in time domain to study transient behavior during frequency acquisition and tracking. Here we utilize a basic PLL system that consist a multiplier, used a...