Δ˰λϼΨϟ΍ : ΖΒδΘϛ΍ ΪϘϟ ΓΩΪΤϣ ΕΎϘϴΒτΗ ϲϓ ΔμΘΨϤϟ΍ ΕΎΠϟΎόϤϟ΍ (ASIPs) ϲϓ ΔϴΒόη ϝΎΠϣ ΝΎΘϧ· ϟ΍ ϖ΋Ύϗή ϥ΄θϟ΍ Ϯϫ ΎϤϛ ϲϓ ρΎγϭϷ΍ ΔϴΜΤΒϟ΍. ϓ ϲϬ (ASIPs) ˱ ϼΣ ήϓϮΗ ˱ ΎόΟΎϧ ˱ ΎϘϓϮϣ ϦϴΑ Γ˯ΎϔϜϟ΍ ΔϧϭήϤϟ΍ϭ ΔΠϣΪϤϟ΍ ΔϤψϧϸϟ ΔΒδϨϟΎΑ ASIP ΪόΘϣ ήΧ΁ ϭ Ω ΠϟΎόϤϟ΍ ΕΎ. 4 ABSTRACT Application-Specific Instruction-set Processors (ASIPs) have gained popularity in production chips as well as in the research community. They offer ...

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major...

In this presentation, several verification problems in configurable processor design synthesis are illustrated. Our research group (PEAS Project) has been developing a novel design methodology of configurable processor, that includes higher level processor specification description, HDL description generation from the specification, Flexible Hardware Model (FHM) for resource management for HDL ...

0272-1732/00/$10.00  2000 IEEE The press and the technical community have generated much excitement and speculation about the IA-64 instruction set and the Itanium processor. Intel and HewlettPackard have rolled out (one instruction at a time) the instruction set. Intel is rolling out (one transistor at a time) the Itanium processor and other platform components. This special issue provides th...

H ighly specialized embedded computer systems abound, and workloads for computing devices are rapidly changing. General– purpose processors are struggling to efficiently meet these applications’ disparate needs, and custom hardware is rarely feasible. The time is ripe for reconfigurable computing, which combines the flexibility of general-purpose processors with the efficiency of custom hardwar...

Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, "hardwired" and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss its imple...