This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy eff...

By using two main effects of cross-gain modulation and cross-phase modulation in semiconductor optical amplifier-based devices, many logic functions of logic AND, OR, XOR, NOR and XNOR are successfully demonstrated. Also, complex systems including all-optical half and full adders in a combination of multiple logic functions are successfully demonstrated. These functions will provide not only in...

Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows CNNs sustain extreme quantization, binarizing their weights and intermediate feature maps, thereby saving 8-32× memory and collapsing energy-intensive sum-of-products into XNOR-and-popcount operations. We present XNO...

Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations...

We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary l...

This paper reports the complete characterization of additive cellular automata (ACA) that employ xor and xnor logic as the next state function. Compared to linear cellular automata (LCA) [3], which employs only xor logic in its next state function, an ACA display much wider varieties of state transition behavior and enhanced computing power. An analytical framework is developed to characterize ...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

A new test pattern generator to reduce the number of transition at scan input during scan shifting is proposed. The method is based on generating more correlative neighboring bits by interchanging adjacent bits in a test pattern. The proposed work is known as Bit Interchanging Teat Pattern Generator (BI-TPG) and it consists of basic XOR, XNOR, AND gates, 2:1 Multiplexer and a register. The leng...