The evolution of today's application technologies requires a certain level of robustness, reliability and ease of integration. We choose the Fields Programmable Gate Array (FPGA) hardware description language to implement the facial recognition algorithm based on "Eigen faces" using Principal Component Analysis. In this paper, we first present an overview of the PCA used for facial recognition,...

Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular for use within high integrity and safety critical systems. One commonly used coding language for their configuration is the VHSIC Hardware Description Language (VHDL). Whilst VHDL is used for hardware description, it is developed in a similar way to traditional software, and many safety critical software certification stan...

This article deals with a method of image recognition based on neural networks composed of MIN/MAX nodes. The general concepts of the MIN/MAX nodes and the neural networks are outlined. The developed software system is then briefly introduced. Finally, the design of the neural networks in VHDL (VHSIC Hardware Description Language) is presented.

This paper describes a plan to integrate current digital hardware design technology into the computer science hardware curriculum. The project will approach digital hardware design from a perspective familiar to computer science students. Techniques featuring Object Oriented Design (OOD), Object Oriented Programming (OOP), code reuse, rapid prototyping, project centered learning, and visualizat...

An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...

Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC Hardware Description Language (VHDL), we demonstrate a computer-aided schematic capture workflow for modeling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations...

This paper presents Cyclic code Encoder and Decoder with its soft core design as well hardware implementation on FPGA. The design includes both encoder and decoder part that can be used in a communication system for encoding a message at the transmitter and decoding it, detecting error and correcting it on the receiver part. The source code for Encoder and Decoder has been formulated in VHDL ( ...

Architecture. The development of a flexible very-large-scale integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, we has develop on a random number generator (RNG), crossover, and mutation based on flexibility structure. This structure can dynamically perform to the 3 types chromosome encoding: binary encoding, real-value encoding, and integer encoding. The ...

VHDL-AMS, or VHSIC Hardware Description Language Analog & Mixed Signal Extensions is being supported in a variety of Design Automation tools for circuit design. Although there are a number of published examples on the use of VHDL-AMS for modeling of mixed signal circuits, it is still not clear what are examples of "best practice" methods. This paper discusses research efforts to identify analog...