A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circui...

This paper investigates the use of floating gate MOS devices for analog trimming. A floating gate MOSFET structure, in which tunneling occurs at the corners of a polysilicon slab, has been fabricated using a standard 1.2p.m n-well CMOS process. The analog storage performance of the floating gate is evaluated. A threedimensional device simulator, DAVINCI, is used to characterize the field enhanc...

A log-domain current-mode true RMS-to-DC converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. The circuit employs floating gate MOS (FG-MOS) transistors operating in weak inversion region. The converter features low power(

a log-domain current-mode true rms-to-dc converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. the circuit employs floating gate mos (fg-mos) transistors operating in weak inversion region. the converter features low power(<1.5uw), low supply voltage (0.9v), two quadrant input current, immunity from body effect, low ci...

A model for the delay of neuron-MOS (neuMOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS [l] and CTL gate structures [a]. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function o...

Implementation of silicon-quantum-dots (Si-QDs) as a floating gate in metal-oxide-semiconductor field-effect transistors (MOSFETs) has received increasing attention because of its potential advantage for multivalued memories operating reliably even at room temperature and above [1-3]. In this work, we focused on electron storage in Si-QDs stack structures and studied electron charging, discharg...

In this paper we present a SPICE-compatible macro model based on three MOS transistors to describe split-gate non-volatile memory (NVM) cell characteristics for various sizes of the gap between the gates. The model has initially been developed based on simulated dc-IV-characteristics of reference cells (floating gate connected to control gate) and was verified later with measurements on referen...

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in:...