Five 8- to 10-year-old children with dysphonetic and dyseidetic dyslexia were given instruction in reading comprehension using a story grammar strategy in which story instruction was differentially designed to match the simultaneous or sequential mental processing strengths of each dyslexia subtype. A multiple baseline, single subject experimental design and statistical analyses indicated that ...

A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss time. We describe a software cache system implemented using dynamic binary rewriting and observe that the combination is particularly appropriate for the scenario of a simple embedded system connected to a more powerful...

Instruction scheduling is a fundamental step for a mapping an application to a computational device. It takes a behavioral application specification and produces a schedule for the instructions onto a collection of system processing units. The objective is to minimize the completion time of the given application while effectively utilizing the computational resources. The instruction scheduling...

The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data trans...

This research analyzed the feedback delivered by cooperating teachers and university supervisors in an internship, and reports how student teachers perceived the feedback they received during debriefing sessions with their mentors. Hattie and Timperley's (2007) framework for conceptualizing effective feedback was used to analyze cooperating teachers' and field supervisor' assessment of the stud...

We present evidence that neurons in the lateral intraparietal area (LIP) of monkey posterior parietal cortex (PPC) are activated by the instruction to make an eye movement, even in the complete absence of a spatial target. This study employed a visually guided motor task that dissociated the type of movement to make (saccade or reach) from the location where the movement was to be made. Using t...

Reconfigurable instruction set processors can potentially reduce the power consumption of high performance multimedia applications by fusing the concept of a reconfigurable array with a programmable processor. In particular, VLIW processors with coarse-grained reconfigurable functional units are specially suited to low power multimedia applications. Code generation for this type of processors i...

Spatial relations can be represented categorically, by means of abstract labels, or coordinately, in metric, absolute measures. These representations have been associated to the left and the right hemispheres respectively (Kosslyn, 1987). Recent studies have focused on the temporal dynamics of spatial relation processing, with working memory task designs. In this light, we examined the suggeste...

In this study, we explore sequential and parallel processing architectures, utilizing a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a singleand a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing c...