سند علمی

Analysis and Optimization of Series-Gated CML and ECL High-Speed Bipolar Circuits

چکیده

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level seriesgated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.

اسناد مشابه