High-level or behavioral synthesis of digital circuits ooers an eeective way to deal with the increasing complexity of digital hardware design. A high-level synthesis tool transforms an abstract algorithmic description into a detailed register transfer level implementation. Since most of the times the algorithmic description is given in textual form, high-level synthesis transformations share c...

It is explained a computational tool, PyHDL, conceived to assist the designer of custom processors. PyHDL takes a description given in Python, an extremely friendly language that allows writing descriptions as close to natural language descriptions as possible with current technology in programming languages. The tool carries out the generation of a synthesizable VHDL equivalent of the descript...

design loop, which covers a large number of design steps (called synthesis loop in figure 1). Therefore, a single cycle of the design loop is quite expensive to perform. Our approach to face this problem is to cut the design loop on a high level of abstraction by integrating a high-level estimation step. This results in a design loop which is tight and settled on high level of abstraction (call...

Abstrac t: Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective way to deal with the increasing complexity of digital hardware design. A high level synthesis tool transforms an abstract algorithmic description into a detailed register transfer level implementation. Even though considerable research has taken place, regarding high-level synthesis,...

High level synthesis is the process of generating register transfer (RT) level designs from behavioral speciications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems 1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it ...

The term High Level synthesis refers to the generation of register transfer level designs from the user defined behavioral specifications in an automatic manner. The main goal of the HLS is to generate a RTL level design that implements the specified behavior while satisfying the design constraints and optimizing the given cost function. High level synthesis is used in image processing because ...

This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated togethe...

This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other software functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread ...