This paper introduces a new design of penternary inverter gate based on graphene nanoribbon field effect transistor (GNRFET). The penternary logic is one of Multiple-valued logic (MVL) circuits which are the best substitute for binary logic because of its low power-delay product (PDP) resulting from reduced complexity of interconnects and chip area. GNRFET is preferred over Si-MOSFET for circui...

As single electron tunneling technology based threshold logic gate uses less no of tunnel junctions so it reduces the size of Boolean logic gate compare to single electron tunneling based logic gate and single electron transistor based logic gate. The design and simulation of a 4:1 multiplexer based on buffered threshold logic gate is presented in this paper. The logic operation is verified usi...

Chronolog(MC) is a logic programming language based on a linear-time temporal logic with multiple granularity of time. In this logic, all formulas can be clocked and are allowed to be deened on local clocks. Therefore the language is exible and it is suitable for modeling and specifying those systems where the notion of dynamic change is central. This paper presents a knowledge-based modeling m...

 The DSCH program is a logic editor and simulator designed by a research group under the leadership of E.Sicard, a professor of INSA of Toulouse . DSCH is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design a...

The aim of this paper is to show how to do social simulation in logic. In order to meet this objective we present a dynamic logic with assignments, tests, sequential and nondeterministic composition, and bounded and non-bounded iteration. We show that our logic allows to represent and reason about a paradigmatic example of social simulation: Schelling’s segregation game. We also build a bridge ...

1991 Abstract A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulllling the system speciication will produce a particular response to a sequence of simulation commands. This style of veriication has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the low-level details of...

This paper describes the impact of DRAM process on the logic circuit performance of Memory Logic Merged Integrated Circuit and the alternative circuit design technology to o set the performance penalty Extensive circuit and routing simulations have been performed to study the logic circuit performance degradation when the merged chip is implemented on DRAM process Three logic processes m m and ...

This paper considers the problem of adaptive output feedback tracking control for a class of nonstrict-feedback nonlinear systems with unknown time-varying delays and unknown backlash-like hysteresis. Fuzzy logic systems are used to estimate the unknown nonlinear functions. Based on the Lyapunov–Krasovskii method, the control scheme is constructed by using the backstepping and adaptive techniqu...