Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map diverse applications onto RPCGRA is difficult due a number hardware constraints. To solve this problem, nodes data flow graph must be partitioned scheduled RPCGRA. In paper, we present Depth-First Greedy Mapping (DFGM) t...
