A 64 X64-bit iterating multiplier, the Stanford Pipelined Iterative Multiplier (SPIM), is presented. Tbe pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a p...

In this paper we present a low power temporal-difference image sensor with wireless communication capability designed specifically for imaging sensor networks. The event-based image sensor features a 64 64 pixel array and can also report standard analog intensity images. An ultra-wide-band radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rat...

Recent industry developments mark a milestone in the evolution of 64-bit computing. 64-bit computing has been around for a long time in mainframe, reduced instruction set computers (RISC), and, more recently, in Intel IA-64 Itanium® architectures. Now, 64-bit computing is being standardized and driven into volume markets by AMD and Intel in processors that are based on the mainstream x86 archit...

8 9 Abbreviated title: Retinoic-acid induced changes in neuronal firing 10 Corresponding Author: 11 G.E. Spencer, 12 Dept. Biological Sciences, 13 Brock University, 14 St. Catharines, 15 ON. Canada. L2S 3A1 16 Tel: 905 688 5550 ext 3391 17 Email: [email protected] 18 19

This paper presents a 64×64 pixel micro-bolometer based temporal contrast IR sensor. The pixels of the sensor independently and asynchronously respond to changes in thermal IR radiation and communicate respective events via arbitrated AER. A 46dB-gain, small-area, ultra low-power, low-mismatch differencing switched-capacitor amplifier has been designed for reading out the bolometer front-end. T...