This paper describes a translation of a relational hardware description language into a functional language in such a way that the user does not have to decide the direction of the data flow in the functional language. This approach relies on laziness, making the translation hard to analyse. The use of a theorem prover that supports reasoning about laziness and undefined elements allows the inv...

This paper proposes, a hardware implementation of Wireless Mesh Networks (WMN) medium Access Controller (MAC) layer transmitter. In the literature a lot of works are focused on WMN routing protocol as well as performance analysis and software integration of WMN units, however few works deals with WMN hardware implementation. In this field our contribution is to conceive and to implements on FPG...

We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VH...

Boolean comparison is a design verification technique in which two logic networks are compared for functional equivalence using analysis rather than simulation. Boolean comparison was used on the IBM 3081 project to establish that hardwareflowcharts and the detailed hardware logic design were functionally equivalent. Hardware flowcharts are a graphic form of a hardware description language whic...

  Drawing on recent developments in linguistic description and applied linguistics, it can be concluded that learning a language necessitates getting to know something and being able to do something with that knowledge: competence, and performance. Structural approach to language description attaches importance to the former; communicative approach to the latter. Appropriate classroom discours...

The RAMP (Research Accelerator for Multiprocessors) project is developing infrastructure to support high-speed emulation of large scale, massively parallel multiprocessor systems using FPGA platforms. In this paper, we describe our proposal for a RAMP Design Framework (RDF), which has a number of challenging goals. The framework must support both cycle-accurate emulation of detailed parameteriz...

The specification of an embedded system at system level together with co–joint hardware/software synthesis is a goal of many rapid prototyping projects. SDL has been proposed as a formal and abstract specification language well suited for this purpose. In the automated generation of hardware however, SDL’s asynchronous communication model (directly implemented in the so called server model) can...

Dynamically re-programmable hardware (e.g. Field Programmable Gate Arrays or FPGAs) change many of our basic assumptions of what hardware is. Normal hardware design focuses on the development of a static circuit of xed size, topology and functionality. The static nature of the target design entity is re ected in the design of CAD tools, hardware description languages, net-list representations a...

The paper focuses on the synthesis of a highly parallel reconfigurable hardware implementation for the International Data Encryption Algorithm (IDEA). Currently, IDEA is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as military, requires efficient, highly reliable and correct hardware implementation. We will stress the affordabil...

Emerging applications mostly require both, high performance as well as support of a wide variety of communication services. For example, audio, video, and data transmission may require highly different services, e.g., guaranteed delay, jitter, or bandwidth. An additional challenge arises by the growing demand for multipoint communication services. ATM networks are capable of satisfying the basi...