This paper investigates the effects of Integral NonLinearity (INL) on the performances of both A/D converters and Digital Communication Systems, which exploit Direct Digital Modulation. The performances of both PCM and Sigma-Delta converters affected by INL are considered and compared. Then, the effects of INL upon the BER performances of an OFDM system are evaluated and modeled. The accuracy o...

4-bit high speed R-2R Ladder Digital to Analog Converter (DAC) design is presented in this paper. The high speed DAC design uses a high speed InGaAs/GaAs HEMT device in its summer block. This paper justifies the use of HEMT devices for high speed converter applications. A detailed analysis of the DAC parameters and errors is presented. DAC performance up to 20GHz is presented and it shows very ...

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. Mismatches among channel ADCs degrade SNR and SFDR of the ADC system as a whole, and the effects of offset, gain and band...

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with sample-and-hold (S/H) sharing technique and gain-boosted voltage-to-time (VTC) is presented for high-speed wireline communication systems. By one S/H between coarse fine stages in the ADC, input bandwidth as well area power efficiency can be improved without gain error ADCs. Thanks...

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance-ratio quantification design for the linearity test of differential top-plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the ...

This paper construct a family of non-linearity tests based on the distance histogram C(m, ε) underlying Grassberger and Procaccia’s Correlation Dimension (CD), Brock, Dechert and Sheink-man’s (BDS) statistic, Mizrach’s Simple Non-Parametric Test (SNT) and Mayer’s Correlation Dimension Ratio (CDR). Two new elements are introduced. The Þrst is homogenizing the data to the uniform or to the normal...

In this paper, the use of the fast Fourier transform (FFT) test to measure the integral nonlinearity (INL) of analog-todigital (A/D) converters is examined. The derived INL is a linear combination of Chebyshev polynomials, where the coefficients are the spurious harmonics of the output spectrum. The accuracy of the test is examined theoretically, in simulations and in practical devices, particu...

This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed implement proposed architecture. The is manufactured in 22nm FD-SOI process. reduces peak INL errors by 50%, RLM rises from 92.4% 98.5% when PAM4 mode. chip area 0.067mm2, while...

Integral nonlinearity (INL) for pipelined analog– digital converters (ADCs) operating at RF is measured and characterized. A parametric model for the INL of pipelined ADCs is proposed, and the corresponding least-squares problem is formulated and solved. The INL is modeled both with respect to the converter output code and the frequency stimuli, which is dynamic modeling. The INL model contains...