this paper presents a new method to reduce consumption power in flash adc in 65nm cmos technology. this method indicates a considerable reduction in consumption power, by removing comparators memories. the simulations used a frequency of 1 ghz, resulting in decreased consumption power by approximately 90% for different processing corners. in addition, in this paper the proposed method was desig...

In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...

this paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology. Two priority encoder approaches are presented, one with semi custom and the other with full custom. The main objective is to compare semi custom and full custom designed layout on the basis of two parameters which is power and area. Both the semi custom circuit simulation and ...

The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Technology Model (BPTM) for 65nm. For the oscillator-based digital sensor presented, a sensitivity ...

We present a comprehensive review of product level reliability challenges for the 65nm technology node. The major reliability degradation mechanisms are analyzed for CMOS technologies. Historical data will show that hot carrier degradation has lost on importance and that negative bias temperature instability (NBTI) is the leading reliability concern for the 65nm technology node. Additionally, d...