We introduce a high-level synthesis methodology to automatically synthesize asynchronous circuits from a concurrent language called ALEPH. ALEPH is a high-level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation, and communication. This specification is translated into a Petri net which has actions. These actions are refined t...

design loop, which covers a large number of design steps (called synthesis loop in figure 1). Therefore, a single cycle of the design loop is quite expensive to perform. Our approach to face this problem is to cut the design loop on a high level of abstraction by integrating a high-level estimation step. This results in a design loop which is tight and settled on high level of abstraction (call...

We address the problem of control synthesis for pipelined data paths. Two basic control schemes are possible: datastationary and time-stationary. In this work, we consider the latter approach. We developed an approach to automatically synthesize time-stationarycontrollers for pipelined data paths produced by high level synthesis tools. A highly optimized FSM controller is implemented using eith...

We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs (CDFGs) during the high-level synthesis of datapath intensive applications. Timing parameters in such CDFGs include the sample period, the latencies between input-output pairs, the relative times at which corresponding samples become available on different inputs, and the relative t...

This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based flo...